Complex computer systems are often designed using multiple boards pluggable into a backplane. A backplane is generally understood to be a common circuit board for receiving multiple cards/boards pluggable into it. A backplane typically carries to the other boards plugged into it power distribution lines and bus signals for inter-board communication. A backplane is usually made as a printed circuit board with several connectors electrically in parallel with each other, so that at least some pins of at least some of the connectors are coupled together, i.e., a pin on one of the connectors is coupled to the same relative pin of other connector(s). A bus is thus formed.
One of the benefits of backplane-based computer system design is the capability to provide spare boards that can be activated to take over when their corresponding primary (main) boards fail. A fault-tolerant system results when spare boards are plugged into a backplane and a mechanism is included for determining when a board fails and should be replaced with a spare. Fault tolerance is desirable in many applications, for example, in high-reliability military and space environments.
When a spare board is powered, it consumes electrical power and generates heat, without producing any immediate benefit. Therefore, it may be desirable to keep spare boards in the unpowered or “cold” state. When a corresponding primary board fails, the spare board in the cold state may be powered to assume the failed board's functions. Until such time, however, the spare board consumes no (or less) energy, and generates no (or less) heat. Such arrangement is referred to as “cold sparing.”
The peripheral component interconnect bus and its metric counterpart, the Compact Peripheral Component Interconnect (cPCI) bus, are widely used for data interchange between various system components, including boards in multi-board systems. (These buses will be collectively referred to as PCI buses in this document.) For some configurations, particularly those including PCI devices designed for 3.3 Volt operation, the PCI standards specify clamping diodes on input/output (I/O) lines. One clamping diode is inserted between the ground or negative supply rail and an I/O line, to prevent the voltage on the I/O line from swinging much below ground potential. A second clamping diode is inserted between the I/O line and VIO (the I/O voltage or positive I/O supply rail), to prevent excessive voltage overshoots. This is illustrated in FIG. 1, in which a diode 110 clamps to ground the voltage on an I/O line 105 of a bus 101, and a diode 115 clamps the I/O line 105 to the VIO. The clamping diodes 110 and 115 thus protect the input of a buffer 120 from under- and over-voltages that may occur on the I/O line 105, for example, resulting from signal overshoot and/or undershoot.
In FIG. 1, the buffer 120 is an input buffer, but a similar arrangement may be employed for output buffers, where the input and output of the buffer are reversed. A similar arrangement may also be employed for bi-directional buffers.
The ground clamping diode 110 is generally needed for current PCI devices, regardless of their voltage range. The VIO clamping diode 115, however, is generally needed for PCI devices designed for 3.3 volt operation, but it may be unnecessary for devices designed for 5 volt operation. This is a consequence of the smaller geometries in the lower-voltage rated devices, which make such devices more susceptible to damage from exposure to higher voltages.
The conventional cold sparing approach is to power off the entire chip or board, so that the I/O lines of the chip or board are tristated. This approach is incompatible with PCI buses that require VIO clamping diodes (e.g., the diode 115), because the VIO clamping diode effectively clamps its corresponding communication line (e.g., the I/O line 105) to ground potential when the VIO power supply line is at ground potential. It should be noted that the VIO clamping diode affects not only the particular device that it protects, but all other devices having PCI I/O lines connected in parallel with the corresponding I/O lines of the protected device, because it effectively shunts to ground all the corresponding lines of the PCI bus to which the protected device is connected, precluding exchange of data over the PCI bus and possibly increasing power consumption.
It would be desirable to allow the use of PCI and similar devices and buses in cold sparing configurations, and to do so without sacrificing the over-voltage protection afforded by the VIO clamping diodes.